1. Field
Example embodiments relate to a method of writing/reading data into/from a memory cell and a page buffer. More particularly, example embodiments relate to a method of writing/reading data into/from a memory cell and a page buffer using different codes for writing and reading operations.
2. Description of the Related Art
Non-volatile memory devices, which can electrically erase and program data, generally preserve stored data even without a power supply. A representative example of a non-volatile memory device is a flash memory.
Memory cells of a flash memory are generally composed of cell transistors. Each cell transistor includes a control gate, a floating gate, a source, and a drain. A cell transistor of a flash memory can be programmed or erased using the Fowler-Nordheim (F-N) tunneling mechanism.
An erasing operation of the cell transistor may be performed by applying a ground voltage to the control gate of the cell transistor and applying a higher voltage than a source voltage to a semiconductor substrate (referred to herein as a bulk) of the cell transistor. During this erasing operation, a strong electric field is formed between the floating gate and the bulk due to a large voltage difference therebetween and thus, electrons stored in the floating gate are emitted to the bulk due to the F-N tunneling effect. Accordingly, a threshold voltage of the cell transistor is reduced.
A programming operation of the cell transistor may be performed by applying a higher voltage than the source voltage to the control gate and applying the ground voltage to the drain and bulk. During this programming operation, electrons are injected to the floating gate by the F-N tunneling effect. Accordingly, the threshold voltage of the programmed cell transistor is increased.
A mode in which electrons are injected to the floating gate is referred to as a programming mode, and a mode in which electrons are removed from the floating gate is referred to as an erasing mode. The threshold voltage of the programming mode may be greater than 0 volts and the threshold voltage of the erasing mode may be less than 0 volts.
Recently, research has been actively conducted on a multi-level flash memory which stores a plurality of data in a memory cell in order to further improve integration density of a flash memory. Multi-bit data including two or more bits may be stored in the memory cell of a multi-level flash memory. A memory cell storing multi-bit data is referred to as a multi-level memory cell while a memory cell storing a single bit is referred to as a single-level memory cell. Since a multi-level memory cell stores multi-bit data, the multi-level memory cell has four or more threshold voltage distributions, as well as four or more storage states of the data corresponding to the threshold voltage distributions. A conventional example of storing two-bit data in a multi-level memory cell of a multi-level flash memory is described below. However, three or more bit data may also be stored in the multi-level memory cell of a conventional multi-level flash memory.
A conventional multi-level memory cell may have a variety of threshold voltage distributions based on a number of storable bits. In the conventional example described below, the multi-level memory cell has four threshold voltage distributions. A conventional multi-level memory cell which stores four bits may have sixteen threshold voltage distributions, for example.
The threshold voltage distributions of the multi-level memory cell in this conventional example are mapped to corresponding codes which represent storage states of the data. For example, the four threshold voltage distributions may be mapped to four corresponding codes (‘11’, ‘10’, ‘01’, and ‘00’) for representing two bits.
Writing and reading operations of the multi-level memory cell are performed by using the codes. In particular, the writing operation of the multi-level memory cell is performed by mapping a threshold voltage distribution of the multi-level memory cell to a code (e.g., ‘00’), which represents a storage state of written data. The reading operation of the multi-level memory cell is performed by checking the position of the threshold voltage distribution and reading the code (e.g., ‘00’), which is mapped to the checked threshold voltage distribution.
Conventionally, the writing and reading operations of a general memory cell are performed by using the same codes. For example, if codes of ‘11’, ‘01’, ‘00’, and ‘10’ are used for the writing operation, the same codes of ‘11’, ‘01’, ‘00’, and ‘10’ are also used for the reading operation.
If the codes optimized for the writing operation are used for the writing and reading operations, the number of reading operations has to be increased in order to check positions of the threshold voltage distributions during the reading operations. On the other hand, if the codes optimized for the reading operation are used for the writing and reading operations, threshold voltage variations increase in the writing operation.